As system-on-chip (SOC) becomes increasingly complex, MIM capacitors play an increasingly critical role in on-chip decoupling, voltage regulation, and analog/radio frequency (RF) circuits. A known approach for forming MIM capacitors includes forming the capacitor with two different insulator materials. However, in this instance, a low voltage coefficient of capacitance (VCC) is achieved at the expense of capacitance density.
In addition, high capacitance density, low leakage MIM capacitors using high dielectric constant (high-k) thin films have been successfully used in high performance complementary metal-oxide-semiconductor (CMOS) logic chips to minimize voltage dropping at the power grids. For many CMOS and bipolar process generations, MIM capacitors have also been an important component in analog/RF circuit blocks. While analog/RF MIM capacitors are less demanding in capacitance density and leakage, they have stringent requirements on low series resistance and voltage and temperature coefficients. Moreover, when both decoupling and analog/RF capacitors are required to be placed on the same chip, e.g., SOC, it is very difficult to build one MIM capacitor that meets both decoupling capacitor (DECAP) MIM and analog/RF MIM requirements. Further, integrating two MIM capacitors, one optimized for decoupling and the other for analog/RF, is usually very complicated and costly.
A need therefore exists for methodology enabling the formation of a stacked MIM capacitor structure that can concurrently achieve a low capacitance density, low leakage, and low VCC as well as a low cost integration scheme to fabricate two MIM capacitors, one optimized for decoupling and the other for analog/RF, in a standard CMOS logic process with only one additional mask.